On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

摘要

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique forSRAM-based FPGA. However, one of the main challenges in achieving 100%robustness in designs protected by TMR running on programmable platforms is toprevent upsets in the routing from provoking undesirable connections betweensignals from distinct redundant logic parts, which can generate an error in theoutput. This paper investigates the optimal design of the TMR logic (e.g., bycleverly inserting voters) to ensure robustness. Four different versions of aTMR digital filter were analyzed by fault injection. Faults were randomlyinserted straight into the bitstream of the FPGA. The experimental resultspresented in this paper demonstrate that the number and placement of voters inthe TMR design can directly affect the fault tolerance, ranging from 4.03% to0.98% the number of upsets in the routing able to cause an error in the TMRcircuit.